Cyclone IV FPGA Device FamilyOverview Altera's new Cyclone®IV FPGA device family extends the Cyclone FPGA series leadership in providing the market's lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs.Built on an optimized low-power process, the Cyclone IV device family offers the following two variants:Cyclone IV E-lowest power, high functionality with the lowest cost Cyclone IV GX-lowest power and lowest cost FPGAs with 3.125 Gbps transceivers1Cyclone IV E devices are offered in core voltage of 1.0 V and 1.2 V.fFor more information, refer to the Power Requirements for Cyclone IV Deviceschapter.Providing power and cost savings without sacrificing performance, along with a low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost, small-form-factor applications in the wireless, wireline, broadcast, industrial, consumer, and communications industries.
Cyclone IV Device Family Features
The Cyclone IV device family offers the following features:
Low-cost, low-power FPGA fabric:
6K to 150K logic elementsUp to 6.3 Mb of embedded memory
Up to 360 18 × 18 multipliers for DSP processing intensive applications
Protocol bridging applications for under 1.5 W total power
Cyclone IV GX devices offer up to eight high-speed transceivers that provide:
Data rates up to 3.125 Gbps
8B/10B encoder/decoder
8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface
Byte serializer/deserializer (SERDES)
Wo rd a l i g n e r
Rate matching FIFO
TX bit slipper for Common Public Radio Interface (CPRI)
Electrical idle
Dynamic channel reconfiguration allowing you to change data rates and protocols on-the-fly
Static equalization and pre-emphasis for superior signal integrity
150 mW per channel power consumption
Flexible clocking structure to support multiple protocols in a single transceiver block
Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1:
×1, ×2, and ×4 lane configurations
End-point and root-port configurations
Up to 256-byte payload
One virtual channel
2 KB retry buffer
4 KB receiver (Rx) buffer
Cyclone IV GX devices offer a wide range of protocol support:
PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)
Gigabit Ethernet (1.25 Gbps)
CPRI (up to 3.072 Gbps)
XAUI (3.125 Gbps)
Triple rate serial digital interface (SDI) (up to 2.97 Gbps)
Serial RapidIO (3.125 Gbps)
Basic mode (up to 3.125 Gbps)
V-by - One (u p to 3 .0 Gb ps)
DisplayPort (2.7 Gbps)
Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)
OBSAI (up to 3.072 Gbps)
Up to 532 userI/Os
LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx
Support for DDR2 SDRAM interfaces up to 200 MHz
Support for QDRII SRAM and DDR SDRAM up to 167 MHz
Up to eight phase-locked loops (PLLs) per device
Offered in commercial and industrial temperature grades
New and original Cyclone V FPGA Device of Altera
Cyclone V FPGA Device Overview The Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption,cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume andcost-sensitive applications.Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitablefor applications in the industrial, wireless and wireline, and automotive markets.
Key Advantages of Cyclone V Devices
Table 1: Key Advantages of the Cyclone V Device Family
Advantage
SupportingLower power consumption
Supporting Feature
• Built on TSMC's 28 nm low-power (28LP) process technology andincludes an abundance of hard intellectual property (IP) blocks
• Up to 40% lower power consumption than the previous generationdevice
Advantage
Improved logic integrationand differentiation capabil‐ities
Supporting Feature
• 8-input adaptive logic module (ALM)
• Up to 13.59 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks
Advantage
Increased bandwidthcapacity
Supporting Feature
• 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
• Hard memory controllers
Advantage
Hard processor system(HPS) with integratedARM® Cortex™-A9MPCore processor
Supporting Feature
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor,hard IP, and an FPGA in a single Cyclone V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherencybetween the processor and the FPGA fabri
Advantage
Lowest system cost
Supporting Feature
• Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol (CvP)and partial reconfiguration
Summary of Cyclone V Features
Table 2: Summary of Features for Cyclone V Devices
Feature
Technology
Description
• TSMC's 28-nm low-power (28LP) process technology
• 1.1 V core voltage
Feature
Packaging
Description
• Wirebond low-halogen packages
• Multiple device densities with compatible package footprints for seamlessmigration between different device densities
• RoHS-compliant and leaded(1)options
Feature
High-performanceFPGA fabric
Description
Enhanced 8-input ALM with four registers
Feature
Internal memory blocks
Description
• M10K-10-kilobits (Kb) memory blocks with soft error correction code (ECC)
• Memory logic array block (MLAB)-640-bit distributed LUTRAM where you canuse up to 25% of the ALMs as MLAB memory
Feature
Embedded Hard IPblocks
Description
Variable-precisionDSP
• Native support for up to three signal processing precisionlevels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) inthe same variable-precision DSP block
• 64-bit accumulator and cascade
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency
Memory controller
DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support
Embedded transceiver I/O
PCI Express® (PCIe®) Gen2 and Gen1 (x1, x2, or x4) hard IPwith multifunction support, endpoint, and root port
Feature
Clock networks
Description
• Up to 550 MHz global clock network
• Global, quadrant, and peripheral clock networks
• Clock networks that are not used can be powered down to reduce dynamic power
Feature
Phase-locked loops(PLLs)
Description
• Precision clock synthesis, clock delay compensation, and zero delay buffering(ZDB)
• Integer mode and fractional mode
Feature
FPGA General-purpose I/Os(GPIOs)
Description
• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
• 400 MHz/800 Mbps external memory interface
• On-chip termination (OCT)
• 3.3 V support with up to 16 mA drive strength
Feature
Low-power high-speed serial interface
Description
• 614 Mbps to 6.144 Gbps integrated transceiver speed
• Transmit pre-emphasis and receiver equalization
• Dynamic partial reconfiguration of individual channels
Feature
HPS( Cyclone V SE, SX,and ST devices only)
Description
• Single or dual-core ARM Cortex-A9 MPCore processor-up to 925 MHz maximumfrequency with support for symmetric and asymmetric multiprocessing
• Interface peripherals-10/100/1000 Ethernet media access control (EMAC),USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI)flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area network (CAN), serial peripheralinterface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
• System peripherals-general-purpose timers, watchdog timers, direct memoryaccess (DMA) controller, FPGA configuration manager, and clock and resetmanagers
• On-chip RAM and boot ROM
• HPS-FPGA bridges-include the FPGA-to-HPS, HPS-to-FPGA, and lightweightHPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves inthe HPS, and vice versa
• FPGA-to-HPS SDRAM controller subsystem-provides a configurable interface tothe multiport front end (MPFE) of the HPS SDRAM controller
• ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage
Feature
Configuration
Description
• Tamper protection-comprehensive design protection to protect your valuable IPinvestments
• Enhanced advanced encryption standard (AES) design security features
• CvP
• Dynamic reconfiguration of the FPGA
• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel(FPP) x8 and x16 configuration options
• Internal scrubbing (2)
• Partial reconfiguration
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